Phani Ramakanth

About Phani Ramakanth

Key Insights:1) Coverage Analysis - code coverage, user cover groups, assertion coverage and RAL coverage.2) SV Assertions for custom bus protocols. 3) Experienced in Test Coding & Debug - Digital, AMS model & Gate Level Simulations. 4) Developing use case Random Test Scenarios & Constraint Random Stimulus. Work Summary: GLS setup, debug and regression closure: mixed signal IP. CPU Verification – Interrupt checks. RAL model: Coverage evaluation, analysis and closure. Verified Register Management Interface Control (RMIC) block. Good at coding functional coverage crosses and closing them. Coded System Verilog assertions Good experience in closing code and functional coverages. Automated flow for Co-simulations (SV+C) though Perl scripts. Verified Transmitter clocking features. Drove verification of Third Party IP configurations and bridge IPs. Verified Serial Packet Interface (SPI) integration for DDR Test Chip.

Experience

1. System Verification Engineer

   Broadcom

   Sep 2018 — Present · Bengaluru, IN

Education

• National Institute of Technology, Tiruchirappalli

  MTech

  2007 — 2009

• Gayatri Vidya Parishad College of Engg., JNTU Hyderabad

  BTech

  2002 — 2006

Skills

• Vhdl
• Simulations
• Pcie
• Ip Integration
• Logic Synthesis
• Static Timing Analysis
• Functional Verification
• Rtl Design
• Systemverilog
• Verilog
• System Verilog