Phani Chalasani
- Role
- Soc Low Power Engineer at NXP Semiconductors
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
Experience
Soc Low Power Engineer
Jun 2022 — Present
Skills
- Mixed Signal
- Low Power Design
- Vhdl
- Digital Hardware Design
- Tcl
- Verilog
- Eda
- Cadence Virtuoso
- Static Timing Analysis
- Perl
- Rtl Coding
- C
- Microarchitecture
- Floorplanning
- C++
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