Phaneendra Sagar
Design Verification Manager, Multimedia
- Role
- Design Verification Manager, Multimedia at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Verification Manager, Multimedia
Nov 2022 — Present · Bengaluru, IN
Education
C-DAC Mohali
Master of Technology, VLSI Design
2009 — 2011
Lakireddy Bali Reddy College of Engineering
Bachelors of Technology, Electronics and Communication
2005 — 2009
Skills
- Ncsim
- Verilog
- Functional Verification
- Assertion Based Verification
- Integrated Circuit Design
- Universal Verification Methodology (Uvm)
- Perl
- Tcl
- Questa
- Atpg
- Static Timing Analysis
- System Verilog
- Rtl Design
- Modelsim
- Vcs
- Debugging
- Formal Verification
- Vlsi
- Asic
- Shell Scripting
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.