Phalguni Bala
Design Engineering Group Director, Memory Interfaces
- Role
- Design Engineering Group Director at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Phalguni Bala
Working in the high speed electrical interface design for about 21 years- Expertise in the memory interface designs, GDDR6/7, HBM2E/3. DDR3/4 - Architected a number of memory interfaces from spec to silicon- Worked on HBMI Tx/Rx, USB2 interfaces- Led AMS teams to execute various PHYs and delivered them successfully on time- Led cross functional teams as CTLE to resolve issues across domains- Hands on experience in layout, RTL coding, STA- Excellent understanding on system design issues- Excellent understanding of package substrate, interposer, PCB designs challenges.
Experience
Design Engineering Group Director
Jul 2025 — Present · Bengaluru, IN
Leading HBM memory interface development.
Education
Indian Institute of Technology, Kanpur
M Tech, Microelctronics
2000 — 2002
University of Calcutta
B.Tech, Radio Physics & Electronics
2000
Skills
- High Speed Link Transceiver Design
- Hslink Analog Back End Design
- Analog Circuit Design
- Analog Mixed Signal Design
- Spice Simulator
- Hslink Analog Front End Design
- Hdmi Transmitter Design
- Knowledge About Digital Design Flow
- Ldo Design
- Hdmi Receiver Design
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