Peter Meyer

Systems & Applications Engineering Manager @Microchip Technology Inc.

CA

Functional manager of Systems Engineering and Applications Engineering within the Timing & Communications Group (TCG).Technology portfolio covers oscillators (XTAL, MEMS, XO, VCXO, TCXO, OCXO), clock distribution (fan-out buffers, zero-delay buffers), clock generation (synthesis, frequency conversion), clock jitter attenuation and clock network synchronization (SyncE, PTP, 1588). Product implementations range from analog to digital, involving hardware, firmware & software.Systems engineering (system architect) team is responsible for new product definition, technical marketing, and development of roadmaps.Applications engineering (customer support) team is responsible for world-wide technical support of Field Applications Engineers (FAE), Tier 1 OEM customer base, and semiconductor or software partners designs. Work is flexible to span from assisting in product validation, coding of software patches, detailed competitive analysis through to authoring application notes, technical reports, technology training videos and providing on-site customer portfolio presentations.As individual contributor, leading or furthering product definition and design-wins with expertise in network synchronization (PTP, SyncE, GNSS, Holdover) spanning the chip, board, equipment, and network levels. Contributing to key timing & synchronization standards setting organizations (ITU-T, 1588). Understanding the application of clocking, timing & synchronization across a wide range of markets including Communications (Telecom, Cable), Enterprise (Financial), Data Center, Industrial, Power, Transportation (Automotive, Aerospace) and Media Audio-Video Broadcast.

Western University

BESc, Electrical and Computer Engineering