Peter Grove

Distinguished Member of Technical Staff @Renesas Electronics

Edinburgh, GB

I have designed many digital blocks, but the key one I am often asked to do is the power management state machine and system startup of ASSP devices. As someone who can use Virtuoso and run Spice/AMS/Digital simulations my mixed signal skills are often needed. I have developed a lot of scripts for digital users to interact if the schematic capture tool without them loading it. As a chair of the Accellera SV-AMS team I take an active role sharing user experience, issues and requests to help guide the standard. I presented for the committee at DVCon 2018 (US) on the current status of SV-AMS. Working with the committee has enabled me to build up a good relationship with key vendors staff. Within Dialog I am recognised as a Verilog-AMS expert to contact and give training on the language to offices Worldwide.As a member of Accellera\'s UVM-AMS I provided the example code and framework that is now been promoted via DVCon. The code utilizes existing standards and ensure that variable passing between the analog and digital solver are done in a predictable fashion. Working in a team of three to design a Digital Mixed Signal (DMS) flow using SystemVerilog User-Defined-Nettypes. The modelling, testbench, API and framework was designed to be vendor agnostic using SV 18••••12 LRM constructs only. Utilizing my knowledge of Verilog-AMS and SystemVerilog a single set of components can be used for DMS and AMS simulations allowing test case to be shared on the same DUT. I have also made the integration into the schematic capture tool seeming less for the users.

The University of Edinburgh

MEng, Electronics