Pentakota Siddhu

Trainee @Maven Silicon

Bengaluru, IN

Undergoing VLSI Design and Verification training at Maven Silicon, Bengaluru. Gained hands-on experience in Verilog and SystemVerilog for RTL design and verification. Skilled in developing UVM-based testbenches, constrained random verification, and functional coverage. Strong understanding of digital electronics, FSM design, and AMBA protocols such as AHB and AXI. Familiar with Static Timing Analysis (STA) concepts and scripting for automation. Experienced in simulation, debugging, and verification methodologies used in the semiconductor industry.