Pengzhao Liu

Computer Architecture Engineer @Black Sesame Technologies Inc

US

Corrected cycle-level behavior of DMA in GEM5 from serial R/W to pipeline R/W access to align with RTL,implemented ports’ mutual block to avoid wrong row tracking and potential data race.• Simulated DRAM Controller access behavior-latency of row activation, pre-charge, row-crossing, andasynchronous clock frequency compared to logic die-based on a simple memory control unit.• Separately handled Write and Read behaviors via DMA and DRAM response mechanism interaction.• Lowered the cycle difference between RTL and GEM5 of the random DMA test from 23% to 3.81%.