Peeyush Purohit

About Peeyush Purohit

With over 22 years of industry experience, I am a CXL Technical Lead at Intel, where I lead the front-end design of CXL and IO Memory Management Unit in Intel Xeon CPUs and other products. I have a Master of Engineering degree in Electronics and a strong technical background in SoC design, verification, and validation.I am passionate about creating innovative and scalable solutions that enable high-performance computing and data transfer. I have successfully delivered the industry\'s first implementation of CXL, a new interconnect standard that reduces latency and improves bandwidth. I have also re-built the IO Memory Management Unit IP from a custom to a standard IP, developing state-of-the-art IP methodologies to support multiple customers within Intel. I believe in building a culture of collaboration and trust among my team and partners, and driving results that are key to Intel\'s success.

Experience

1. Principal Engineer

   Arm

   Aug 2024 — Present · TX, US

   Accelerator Enable Kit (AEK) – Defined & Developed a system with host + accelerator using dual CXL controllers with a single software-visible endpoint, enabling ~2× performance scaling for accelerator workloads. Developed PCIe/CXL subsystem using third party controller, IDE and ARM infrastructure IPs to build end to end solution. Architected and delivered a highly configurable, vendor-agnostic PCIe/CXL Message Handler IP supporting all standard and vendor-defined message types with no architectural constraints.

Education

• Devi Ahilya Vishwavidyalaya

  Bachelor of Engineering - BE, Electronics

  1995 — 1999

• University of Mumbai

  Master of Engineering - MEng

Skills

• Functional Verification
• Asic
• Debugging
• Soc
• Vlsi
• Systemverilog
• Ic
• Rtl Design
• Semiconductors
• Embedded Systems
• Verilog