Peddisetty Rupavathi
Design Verification Engineer | IP & SoC Level | SystemVerilog • UVM • VCS • Verdi • Xilinx
- Role
- Senior Engineer at Happiest Minds Technologies
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Peddisetty Rupavathi
Design Verification Engineer with ~3 years of experience in IP & SoC level verification. Skilled in SystemVerilog, UVM, Synopsys VCS, Verdi, and Xilinx tools. Proven ability to develop scalable testbenches, run regressions, and debug complex RTL designs. Passionate about high-quality silicon and collaborative development. Eager to grow with innovative teams.
Experience
Senior Engineer
Jan 2026 — Present · Bengaluru, IN
Education
G. Pulla Reddy Engineering College
Bachelor's degree, Electronics and Communication Engineering
Jawaharlal Nehru Technological University, Anantapur
Master's degree, VLSI System Design
2022
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