Peter Nguyen
Principal Process Engineer at Microchip
- Role
- Senior Dry Etch Process Engineer at Intel
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
About Peter Nguyen
Dry etch process engineer with extensive experience driving innovation and process excellence across Intel 4, Intel 18A, and Intel 14A tech nodes in the semiconductor manufacturing industry. Specialized in development and optimization of dry etch processes to address challenges related to cost efficiency, yield improvement, variability reduction, and performance enhancement, employing skills such as JMP data analysis and model-based problem solving. Committed to fostering collaborative environments to deliver superior products that exceed customer expectations.
Experience
Senior Dry Etch Process Engineer
Jul 2016 — Present · Hillsboro, OR, US
Developed and optimized front- and middle-end-of-line etch processes. Collaborated with cross-functional teams to solve key integrated issues related to yield and end-of-line mismatches, defect modes, process variability, and high-volume manufacturing (HVM) robustness.· Led vendor selection initiatives across various dry-etch toolsets (i.e. LAM, AMAT, Hitachi, and TEL), achieving significant cost savings for Intel and executing module target specs (MTS).· Involved in process development cycle beginning with early pathfinding to HVM transfer of mature processes.· Piloted advanced process control (APC) systems to reduce process variability. Helped refine operational practices which led to more universal development of APC systems across etch module.· Mentored junior engineers and developed them to be successful in process development and tool/layer ownership.· Spearheaded process quality improvement projects which included sharing quality excursion learnings, creating training documentation for best quality practices, implementing SQL scripts for improved SPC chart monitoring, and leading quality flag reduction efforts.· Qualified and sustained several dry-etch tools including the diagnosis and troubleshooting of station monitor deviations. Recovered chamber capacity from in-line, yield, and end-of-line tool mismatches.· Received 4x Intel Development Department Divisional Awards.· Co-authored six invention disclosures, four which received Intel Distinguished Invention Awards and two which are patent processing.
Education
Virginia Tech
Bachelor of Science (B.S.), Electrical Engineering
2010 — 2014
Virginia Tech
Master of Science (M.S.), Semiconductors
2014 — 2016
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