Patrick James
Computer Chipset Project Engineer – Expert in Client Product Architecture | High-Performance Computing | Cross-functional Team Leader | Mentor | Product Innovator
- Role
- Computer Chipset Project Engineer at 高通
- Location
- Beaverton, OR, US
- LinkedIn followers
- 500 followers
About Patrick James
I am a seasoned and accomplished Senior Principal Engineer & Chief Architect with over 15 years of experience in system and SoC architecture and high-performance platforms with a robust track record in designing, implementing, and scaling cutting-edge technical solutions across complex infrastructures.I showcase vast expertise as a creative and forward-thinking Technical Leader, persistent in delivering next-generation computing solutions by aligning technology roadmaps with business objectives. I drive a focus on scalable systems architecture, power efficiency, and Artificial Intelligence (AI)/Machine Learning (ML) integration.I have successfully led cross-functional teams in developing innovative products, optimizing power/performance trade-offs, and ensuring a seamless integration of technology roadmaps across hardware and software domains.I drive competitive advantage and key decisions that are integral to product definition, while concurrently delivering competitive solutions in high-complexity/high-performance computing environments. I am recognized for mentoring and developing talent, guiding teams through technical challenges, and shaping long-term career growth.In my Career at Intel,I was the Chief Architect, responsible for defining the architecture for Intel 10th Gen Core, 14th Gen Core and Intel Core Ultra products, leading pathfinding for future product development.I was the lead architect for Intel Cable and Media Set-top-box product definition, creating SoC and customer specifications for Cable Modems and spearheading the development of an Intel Branded set-top-box.I led a team to transform how we test and validate high speed interfaces by developing validation tools targeting high speed memory interface, Direect Media Interface and PCIe Graphics interface.As a client memory architect, I led the development of DDR3 and DDR4 specifications, NAND caching, embedded DRAM, and Phase Change Memory. I created methodologies to predict memory power and performance for mobile client segments.Finally, I started my career as a Senior Hardware Engineering for Intel Server group, delivering Silicon Validation and Customer reference designs for Intel Xeon and Intel Itanium processor families.
Experience
Computer Chipset Project Engineer
Sep 2025 — Present · San Diego, CA, US
Education
Oregon State University
Bachelor of Science - BS
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.