Payal Sidpara
ASIC Digital Design Engineer at Synopsys Inc
- Role
- Asic Digital Design Engineer at 新思科技股份有限公司
- Location
- Rajkot, GJ, IN
- LinkedIn followers
- 500 followers
About Payal Sidpara
A highly organized and hard-working individual looking an exciting and challenging entry level position in VLSI industry to gain practical experience. Good knowledge of Verilog, System Verilog, UVM, STA, perl scripting.
Experience
Asic Digital Design Engineer
Feb 2022 — Present · Noida, IN
Education
Dr.S.& S.S.Gandhi college of Engg. And Technology,Surat 612
Bachelor of Engineering, Electronics and communication engineering
2014 — 2018
V.V.P. ENGINEERING COLLEGE, RAJKOT 047
Master of Engineering - MEng, Electronics and communication
2018 — 2020
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