Payal Kalamdar
Design Verification Engineer
- Role
- Design Verification Engineer at Cirrus Logic
- Location
- Chandler, AZ, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Verification Engineer
Feb 2024 — Present · Chandler, AZ, US
Education
S.B. Jain Institute of Technology,Management & Research, Nagpur
Bachelor of Engineering - BE, Electronics and Telecommunication
2017 — 2021
Portland State University
Master of Science - MS, Electronics and Computer Engineering
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.