Payal Asarawala

About Payal Asarawala

19+ Years of experience as ASIC Design and Verification Engineer with SystemVerilog based UVM/OVM/VMM testbenchstrong experience in multi core ARM based SoC verification with cache coherent networks for networking application.@synopsysWorking on verification of Die-to-Die UCIe controller which is key enabler of multidie system.worked on high speed Serdes@HCLworked on ADAS chip with Lidar based system and written test bench from scratch for one of the modules.Worked on Multi-core ARM based SOC with CortexA53Worked on AXI4 and ACE protocol and done A53 subsystem verification worked for CCI400- Debugged and Resolved coherency related issues for SOC.Worked for Israel client for ADAS chip and in worked for Safety event manager, modem pipelined unit.@cyientWorked on Multi-core ARM based SOC.Done verification for GIC400- Interrupt Verification from scratch.Worked on I2C verification at SOC level.@Intelworked on Module level verification of one of the Network processor moduleworked on SOC verification of ARM cortex A53 based subsystem Worked on AMBA-5 CHI protocolWorking on MAC Security @LSIWorked on verification of Network processor at fullchip level and module level with SystemVerilog - LVM/VMM based Testbench @Wipro : Worked on SystemVerilog-OVM and UVM based Verification Worked on Module level verification of Serial RapidIOWorked on Subsystem Verification of ARM cortex -M3 based subsystemo Experience in RTL Verification, Gate Level Simulation (GLS) and Digital Design for ASIC at IP level and Full-Chip/SoC level.@Sasken :o Functional Verification of ARM1176 based subsystem and GLS.o Exposure to Design for Test (DFT), Synthesis and Static Timing Analysis (STA) Specialties: ExpertiseTools: Questa-ModelSim,Synopsys VCSMX, Cadence NC-Sim, Spyglass, Synopsys DFT Compiler, Debussy, TetramaxProgramming languages: SystemVerilog,Verilog, VHDL,C, Assembly LanguageWorked on : OVM, UVM and VMM methodologiesProtocols :SRIO,AXI, AHB, APB, SPI, I2S, I2C,UARTScripting Languages : TCL, Perl, AWK and Sed

Experience

1. Principal Engineer

   Synopsys Inc

   Feb 2025 — Present · Pune, IN

Education

• Sarvajanik College of Engineering & Technology

  B.E., Electronics

  1998 — 2002

• St. Xaviers School Surat

  HSC

  1996 — 1998

• Nirma University

  M.Tech, VLSI Design

  2004 — 2006

• Lourdes Convent High School, Surat

  SSC

  1983 — 1996

Skills

• System on a Chip (Soc)
• I2c
• Ip Verification
• Application-Specific Integrated Circuits (Asic)
• C
• Spi
• Amba Ahb
• Verilog
• Systemverilog Ovm/Uvm Verification
• Arm Cortex
• Gate Level Simulations
• Perl
• Tcl
• Systemverilog
• Synopsys Tools
• Functional Verification
• Asic
• Vhdl
• Uart
• Network Processors
• Soc Verification
• Ncsim
• Universal Verification Methodology (Uvm)