Shivaji Pawar

About Shivaji Pawar

At Google Cloud, as a Physical Design Methodology Lead, Shivaji contributes to industry-leading advancements in low-power and high frequency integrated circuit design and flow automation for AI chips.With over 15+ years of expertise in RTL-to-GDSII physical design across Cloud/Mobile/Data Center/IP/EDA market segments of Semiconductor industry, Shivaji is specialized in developing and optimizing methodologies for EDA, Synthesis, place-and-route, timing closure, Electromigration/IR drop mitigation and low-power design at advanced technology nodes.His work has enabled 15+ successful tape-outs of multi-million transistor chips across industry, demonstrating a strong focus on performance, power, and area improvements on technology nodes ranging from 40nm to lowest technology nodes.Throughout his career, Shivaji has collaborated on cutting-edge physical design flows and contributed to improving PPA-runtime efficiency. By leveraging deep knowledge of tool engine algorithms and automation, Shivaji has consistently driven innovation in ASIC physical design methodologies.Through empathetic and serviceable leadership, Shivaji’s mission is to empower teams to deliver high-quality, high-performance designs while pushing the boundaries of semiconductor technology.

Experience

1. Physical Design Methodology Lead

   Google

   Sep 2024 — Present · Sunnyvale, CA, US

Education

• College of Engineering Pune

  Bachelor of Technology (B.Tech.), Electronics and Telecommunications

  2006 — 2010

• ACVM high school, Malkapur, Karad, India

  Marathi medium high school

  1999 — 2004

• Sadhguru Gadage Maharaj college, Karad, India

  Science

  2004 — 2006

Skills

• Lvs
• Ic
• Ic Validator
• Tcl
• Physical Design
• Eda
• Ic Compiler 2
• Signal Integrity
• Icc
• Primetime
• Backend Development
• Drc
• Waveform Editor
• Primerail
• Asic
• Floorplanning
• Test Chip Implementation
• Pnr
• Very-Large-Scale Integration (Vlsi)
• Shell Scripting
• Rtl Design
• Low Power Design
• Timing Closure
• Prime Rail
• Static Timing Analysis
• Customdesigner
• Calibre
• Vlsi
• Ic Compiler
• Ic Work Bench
• Application-Specific Integrated Circuits (Asic)
• Physical Verification
• Formal Verification
• Clock Tree Synthesis
• Icc2
• Ir Drop Analysis
• Unix Shell Scripting
• Compilers
• Logic Synthesis
• Flow Automation