Pawan Talkad

About Pawan Talkad

Director, Silicon Design Engineering with 22+ years building and leading physical design teams that deliver complex SoCs at advanced nodes.* Lead a cross-site team of 70+ engineers, delivering 30+ tape-outs across 28nm–2nm, optimized for PPA on flagship products and driving end‑to‑end implementation: floorplanning, PnR, STA, power, and sign‑off for high-performance designs.* Partner with architecture, RTL, verification, and package/board teams to balance performance, power, and area while de‑risking schedules for highly competitive market windows.* Build and scale talent: hire, mentor, and grow engineers into tech leads and managers, raising the bar on quality, ownership, and collaboration.* Champion methodology improvements and automation that cut closure cycles, reduce iteration churn, and improve predictability across programs.* Currently focused on shaping and developing next‑generation silicon designs, and driving predictable tape-out execution in an increasingly complex technology landscape.

Experience

1. Director

   AMD

   Jul 2024 — Present · Hyderabad, IN

Education

• Govt. Institute of Electronics

  Diploma, Electronics and Instrumentation

  1998 — 2001

• Om Vidyalaya

  Schooling

  1988 — 1998

• Jawaharlal Nehru Technological University

  B. Tech, Electronics and Communication

Skills

• Asic
• Soc
• Static Timing Analysis
• Vlsi
• Physical Design
• Eda
• Ic
• Floorplanning
• Physical Verification
• Drc
• Lvs
• Semiconductors
• Cadence
• Verilog
• Tcl
• Embedded Systems
• Cmos
• Application-Specific Integrated Circuits (Asic)
• System on a Chip (Soc)