About Pavan Dixit
ASIC Design Engineer skilled at Verilog, Systemverilog, Perl, python, C/C++. Experienced…
Experience
Present
Skills
- Cadence
- Microsoft Visual Studio
- Linux
- Modelsim
- Synopsys Design Compiler
- Unix
- Asic
- Cadence Spectre
- Perl
- Cadence Simvision
- C++
- Microsoft Visual Studio C++
- Verilog
- Pspice
- C
- Cadence Encounter
- Chipscope
- Synopsys Primetime
- Cadence Nc Sim
- Cadence Spectre Simulator
- Xilinx Ise
- Cadence Virtuoso
- Computer Architecture
- Tetramax Atpg
- Functional Verification
- Systemc
- Vhdl
- Matlab
- Ncsim
- Java
- Python
- Cadence Virtuoso Ade
- Synopsys Tools
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