Pavan Kumar Sannidhi

About Pavan Kumar Sannidhi

2 years of RTL Design experience and 13 years of Verification…

Experience

1. Design Verification Engineer

   Meta

   Mar 2021 — Present

Education

• NOVA COLLEGE OF ENGINEERING AND TECHNOLOGY

  B.TECH, EEE

  2003 — 2007

Skills

• - Rtl Debugging
• Rtl Coding
• Systemverilog
• C++
• Perl
• Uvm
• Debugging
• Vhdl
• Functional Verification
• Static Timing Analysis
• Universal Verification Methodology (Uvm)
• Logic Synthesis
• Soc
• - Extraction of Features From Requirement Specification
• Verilog
• - Rtl Synthesis
• - Design & Development of Verification Environment
• System on a Chip (Soc)
• C
• Testing
• Open Verification Methodology
• - Coverage Analysis
• Very-Large-Scale Integration (Vlsi)
• - Rtl Designing
• - Rtl Timing Analysis
• Modelsim
• Rtl Design
• - Testcase Development