Pavan Kumar C.
Timing Methodology Engineer at NVIDIA
- Role
- Pd Timing Methodology Engineer at NVIDIA
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Pd Timing Methodology Engineer
May 2021 — Present
Education
Columbia University
Master of Science - MS, Electrical Engineering
2016 — 2017
Columbia University
Doctor of Philosophy (PhD), Electrical Engineering
2016 — 2021
Indian Institute of Technology, Delhi
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering
2012 — 2016
Skills
- Analog Circuits
- Algorithms
- Robotics
- Labview
- System Verilog Assertions
- Embedded C
- Python
- Image Processing
- C
- Data Structures
- Matlab
- Vhdl
- Theano
- Verilog
- C++
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