Pavan Badiger

About Pavan Badiger

Experienced DFT Engineer and a Graduate student from Arizona State University specialized in VLSI. As a DFT Engineer, I have worked on Scan insertion, ATPG, low coverage analysis and validation of Scan, LBIST and MBIST patterns. With my academic courses oriented towards mixed signal designing, Front-end digital design, standard cell layout, synthesis and Place and Route, I have gained a comprehensive knowledge of ASIC design. My areas of interest include I/O BIST, IJTAG 1687) and DFT for mixed signal designsTools exposure-Synopsys : Design Compiler,Tetramax, DFT compiler and HSPICE.Cadence : RTL compiler, NC verilog, Cadence5, Cadence6, Simvision, and Virtuoso.Mentor Graphics : Tessent Hierarchical Integration flow, Fastscan, Modelsim, Active-HDL : Aldec simulatorLanguages : C, Verilog, System Verilog.Scripting languages : Perl and Tcl

Experience

1. Dft Engineer

   Apple

   Mar 2021 — Present · Austin, TX, US

Education

• PES Institute of Technology

  Bachelor of Engineering, Electronics and communications

  2007 — 2011

• Arizona State University

  Master of Science (MS), Electrical and Electronics Engineering

  2013 — 2015

Skills

• Rtl Design
• Debugging
• Low-Power Design
• Aldec
• Vhdl
• Modelsim
• Vlsi
• C
• Cadence Spectre
• Perl
• Tcl
• Analog
• Mixed Signal
• Memory Test
• Drc
• Dft
• Systemverilog
• Atpg
• Synthesis
• Asic
• Bist
• Logic Synthesis
• Very-Large-Scale Integration (Vlsi)
• Automatic Test Pattern Generation (Atpg)
• Scan Insertion
• Cadence
• Integrated Circuit Design
• Verilog
• Application-Specific Integrated Circuits (Asic)