Pavan Topagi

About Pavan Topagi

VLSI Engineer with hands-on 14nm experience in Physical Design and DFT.Passionate about building high-performance, power-efficient silicon through precise design closure, testability integration, and physical verification. I hold a Master’s degree in Digital VLSI Design and am currently based in Sacramento, CA. My journey blends academic rigor with hands-on project experience in Physical Design (PnR), DFT (Design-for-Test), RTL design, and transistor-level simulations—especially on advanced nodes like 14nm. Core Technical Experience: Physical Design (PnR): Delivered a multi-voltage, multi-clock RISC-V (ORCA_TOP) in 14nm—floorplanning, CTS, timing signoff for 52k+ standard cells and 40+ macros. DFT & ATPG: Integrated scan chains into RTL, generated test patterns using Tessent Scan/ATPG, debugged simulation mismatches, and fixed DRCs. RTL & Circuit Design: Built a 4-bit ALU in Cadence Virtuoso (DRC/LVS clean) and a configurable FIFO controller in Verilog with full functional verification.🧠 Skills Snapshot: Timing Closure, Clock Skew Optimization, Reg2Reg Path Debug LEF/DEF, Tech Files, Placement & Routing Rule Awareness IC Compiler II, Vivado, Calibre, Cadence Virtuoso, Tessent, ModelSim Scripting: Basic Python, TCL | Platforms: Linux What Drives Me:I love working in fast-paced teams that tackle complex design challenges. Whether it’s optimizing timing paths or ensuring testability at scale, I strive to make meaningful contributions to silicon success. Open to full-time opportunities in Physical Design / DFT / Physical Verification. Let’s connect!

Experience

1. Intern Physical Design

   Tenstorrent

   Jan 2026 — Present · TX, US

Education

• Kls Gogte Institute Of Technology Belgaum

  Bachelor of Engineering - BE, Electronics and Communications Engineering

  2015 — 2019

• California State University-Sacramento

  Master of Science - MS, Electrical and Electronics Engineering