Pavan Teja Dama
Design Engineer at AMD
- Role
- Senior Design Engineer at AMD
- Location
- Hyderabad, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Pavan Teja Dama
Familiar with ASIC Design, Full-Custom Design flow & IC Fabrication process -Hands…
Experience
Senior Design Engineer
May 2018 — Present · Hyderabad, IN
Education
Sri Chaitanya College, Tirupati
Juniar College
2006 — 2008
Chadalawada Ramanna Engineering College
Bachelor’s Degree, Electronics and Communications Engineering
2008 — 2012
Sudhaha School, Tirupati
High School
1996 — 2006
Sri Venkateswara College of Engineering
Master’s Degree, VLSI design
2013 — 2015
Skills
- Memory Layout Design
- Layout Versus Schematic (Lvs)
- Back End
- Dft
- Standard Cell Characterisation
- Low Power Design
- Physical Verification
- Analog
- Dfm
- Semiconductors
- Management
- Very-Large-Scale Integration (Vlsi)
- Electronics
- Ic Layout
- Verilog
- Ic
- Analog Layout Design
- Cmos
- Lvs
- Caliber
- Integrated Circuits (Ic)
- Shell Scripting
- Perl
- Digital Circuit Design
- Drc
- Analog Circuit Design
- Vlsi
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