Pavan Malbhage
Staff Layout Engineer at Synopsys
- Role
- Staff Layout Engineer at 新思科技股份有限公司
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Pavan Malbhage
8+ years of experience in Analog/RF/SERDES/IO Layout Domain-Familiar with Custom Cell Layout Design-Have Experience in layout designing of Low Dropout Regulator (LDO), Band Gap Reference (BGR), Comparator, Two stage Amplifier (Op-amp), Buffers, Low Noise Amplifier (LNA)- Independently handled project of Testchips-Technology Exposure: 2nm, 4nm, 28nm, 45nm, 130nm, 180nm-Able to design the layouts by following ESD and Latch-up rules with proper floor planning, Layout Verification and Error analysis- Capable to design area & route efficient layouts with less parasitic/complexity/ delay/coupling/EM etc-Knowledgeable with CMOS Fabrication Process, ASIC Flow and Physical Design Flow-Proficient in IC verification checks like DRC, LVS, Antenna Checks- Knowledgeable with IR Drop, Electro-migration, Crosstalk, Latch-Up, ESD, Antenna Effect, WPE, basics of Deep N-Well, STI effects-My strengths are Self-Confident, Flexibility to try New Approaches and Adaptable with any tool within minimum time.
Experience
Staff Layout Engineer
Aug 2024 — Present
Education
Sinhgad Academy Of Engineering, Pune
Bachelor of Engineering (BE)
MIT College of Engineering, Pune
Master of Engineering (ME)
Skills
- Microsoft Office
- Management
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