Pavan M
Hardware Design verification Engineer
- Role
- Senior Design Verification Engineer at Wipro
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
Information TechnologyView LinkedIn profile
About Pavan M
Have Experience in Functional Verification IP and SOC level. Worked on 10G/1G Ethernet, 10G MAC, Arm AMBA bus protocols AHB,APB.Skilled at Verilog (RTL coding), System Verilog, Assertion,Functional and code coverage analysis, UVM,Digital concepts,Perl,basics C and python(beginner).
Experience
Senior Design Verification Engineer
Nov 2021 — Present · Bangalore Urban, IN
Bangalore Urban, Karnataka, India
Education
Visvesvaraya Technological University
Bachelor of Engineering
2012 — 2016
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