Pavan Kumar Mantravadi
Googler
- Role
- Full Chip Design Verification Engineer at Google
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Pavan Kumar Mantravadi
10+ Years of experience in IP/SoC functional verification.
Experience
Full Chip Design Verification Engineer
Dec 2022 — Present · Bengaluru, IN
Education
Sri Sri Vidyanikethan
Primary Education
1997 — 2001
Little Buds Public School
Secondary Education
2001 — 2005
Sri Chaitanya Bharathi Junior College
Intermediate, Maths Physics and Chemistry
2008 — 2010
Ravindra Bharathi Public School
Secondary School Education
2005 — 2008
Skills
- Computer Hardware
- Usb3.0
- Uvm
- Leadership
- Powerpoint
- Microsoft Excel
- Matlab
- Rtl Design
- Very-Large-Scale Integration (Vlsi)
- Rtl Verification
- C
- Programming
- Verilog
- Functional Verification
- Application-Specific Integrated Circuits (Asic)
- Unix
- Perl
- Asic
- Microsoft Office
- Vlsi
- Modelsim
- Design Verification Testing
- Management
- Soc
- Microsoft Word
- Electronics
- Digital Electronics
- Synopsys Tools
- Vhdl
- Simulations
- System on a Chip (Soc)
- Testing
- Xilinx
- Systemverilog
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