Pavan Chopade

About Pavan Chopade

Enthusiastic and self motivated physical design engineer with experience in handling various physical design steps from RTL to GDSII flow for advanced technology nodes. Experience in independently handling and supporting block as well as TOP level physical design implementation for technology nodes ranging from 130nm,110nm,65nm to 28nm,16nm,7nm,6nm,5nm and 3nm Experience of firmware development and integration for various in house projects and client based projects at LinkedLoops.Also experience of working on site for our Singapore based client for 1 month duration Good leadership skills and experience of handling system level projects. Consistent performance in Academics,Co-curriculars and Extra-curriculars.

Experience

1. Staff Engineer Asic Physical Design

   Synopsys Inc

   Feb 2024 — Present · Pune, IN

Education

• Bal Vidya Mandir Highschool,Nanalpeth,Parbhani

  SSC

  2005 — 2011

• Walchand college of engg.,Sangli

  Bachelor of Technology (B.Tech.), Electronics Engineering

  2013 — 2017

Skills

• Verilog
• C
• Timing Closure
• Static Timing Analysis
• Logic Synthesis
• Powerpoint
• C++
• Clock Tree Synthesis
• Firmware
• Leadership
• Embedded Systems
• Microsoft Office
• Management
• Html
• Physical Design
• Teaching
• Electronics
• Microsoft Word
• Synopsys Prime Time
• Research
• Place and Route
• Java
• Rtl Design
• Digital Design
• Design Compiler
• Ic Compiler
• Vlsi Design
• Public Speaking
• Floorplanning
• Unix
• Computer Architecture
• Field-Programmable Gate Arrays (Fpga)
• Customer Service
• Shell Scripting