Paulpandi K

About Paulpandi K

Skilled in VLSI physical design with hands-on experience in over 20 successful tape-ins and tape-outs across advanced technology nodes* Expertise in complete back-end PnR flow, spanning RTL-to-GDSII with a focus on high-performance designs* Proficient in sub-FC/Sub-system level Design Planning, partitioning and integration* Extensive experience in Synthesis, floor planning, power planning, placement, clock tree synthesis, routing, extraction, IR drop analysis, timing, signal integrity closure, and ECO flows for complex and low power designs* Skilled in tackling advanced technology nodes, ranging from 7nm to 180nm, for diverse design challenges* Hands-on with cutting-edge EDA tools, including SoC Encounter, ICC1/ICC2, Fusion Compiler, PrimeTime, PT-ECO, Design Compiler, Conformal, Tweaker, and Redhawk* Strong exposure to timing signoff, physical verification, and LEC* Experienced with low power ASIC design implementation techniques* Expertise in Clock Tree Synthesis (CTS) and Static Timing Analysis (STA)* Skilled in automation using TCL scripting* Efficient in ECO flows across various technology nodes, ensuring swift and accurate design closure

Experience

1. Soc Design Engineer

   Intel

   Dec 2018 — Present · Bengaluru, IN

Education

• Anna University Chennai

  Bachelor of Engineering (BEng), Computer Science

  2005 — 2009

Skills

• Physical Verification
• Drc
• Floorplanning
• Layout Versus Schematic (Lvs)
• Asic
• Vlsi
• Tcl
• Timing Closure
• Clock Tree Synthesis
• Mixed Signal
• Design Rule Checking (Drc)
• Static Timing Analysis
• Verilog
• Physical Design
• Place & Route
• Lvs