Patrick Conti

About Patrick Conti

Experienced Chip Lead Mask Designer for Analog & RF with experience in 28nm and 20nm, 16nm & 14nm finfet layout. In my RF World though, we live in the SOI processes where I have over 25 tapeouts.Short Story:Seven years as LNA Chip LeadFifteen plus years full custom Analog & RF LayoutTwo years SRAM layout. Layout done in CMOS down to 14nm finfet. Performed cell level layout through full chip & tapeout. Experienced user of industry standard tools from Cadence, Mentor and Synopsis including-Virtuoso 6.1.x using Assura and VXL-Calibre DRC/LVS including RealTime-ICValidator and Hercules. Experienced using in-house layout tools such as Unified Editor Layout tool (Avago/Broadcomm). Experienced working in foundry PDKs from TSMC, Samsung, Global Foundries, IBM and UMC. Experience with BiCMOS & Bipolar technologies in the past. Details:2017 - Present: Chip Lead for LNA chips of up to ~90 bumps - Floorplanning, scheduling, Analog & RF layout and last but not least, directing local and geographically remote layout resources from initial floorplan through tapeout. Just as important, working with Circuit designers to determine appropriate trade-offs for the available space and ultimately to achieve schedule objectives. 25+ Successful Tapeouts Prior experience; Module lead directing remote and local layout resources for a first time gigahertz product along with a high current module. Met the schedule and performance required.Module Lead for Analog Clocking Block supplying clock signals to the rest of a large RF chip. Past experience : Created and/or re-worked layouts of Macros for larger chip teams throughout my career including QLNA, WLAN, DAC, ADC, GNSS and SERDES, most recently at Qualcomm (28nm,20nm, 14nm and larger RF geometries) and Avago/Broadcomm (16nm finfet). Independent layout and tapeout of full chips for Temperature Sensor, Amplifier and ADC groups at National Semiconductor. IC level Failure Analysis experience as well.I enjoy Leading teams for full chip layout along with laying out macros and integrating that work into a larger chip team. I enjoy debugging a layout when needed and value a strong methodology in the layout flow.Last, but certainly not least, a positive and \"can do\" approach to work and life.Specialties: A solid foundation in Analog/Mixed Signal Layout techniques. Strong verification & debugging skills. A history of improving methodology and communication within work groups and across teams.

Experience

1. Staff Mask Designer-chip Lead-analog

   美商高通國際股份有限公司

   May 2015 — Present · San Diego, CA, US

   RF/Analog Layout: Chip Lead for the LNA chips we build as Stand Alone solutions or as part of a Qualcomm system solution. In that role, I work with the circuit designers to establish the initial floorplan, put together a schedule, request headcount, lead direct reports onsite and at different geographic locations, coordinate the evolving footprint and circuit trade-offs with the Circuit Design Lead and hold layout reviews at intermediate and final stages. Once that is accomplished, complete all tapeout activities including population of tapeout libraries, schematic and layout, full verifications of circuitry and physical correctness, all necessary XOR and finally creation of a foundry GDS to be shipped to the appropriate foundry.Work for the past 8 years has been the position of Chip Lead, described above. Prior to that, module to block level responsibilities.

Education

• Colorado Technical University

  ASET -Associates Electronic Technology, Electronics, Telecom

  1997

Skills

• Rf
• Drc
• Hercules
• Virtuoso
• Sram
• Cadence Virtuoso
• Floorplanning
• Bicmos
• Power Management
• Lvs
• Cadence
• Ic
• Debugging
• Low-Power Design
• Eda
• Mixed Signal
• Calibre
• Layout Versus Schematic (Lvs)
• Serdes
• Cmos
• Ic Layout
• Design Rule Checking (Drc)
• Analog