Akhilesh P.

About Akhilesh P.

Digital Design Engineer with experience in ASIC Design, Memory Design and Verification- Developed a tool and methodology to predict SRAM yield using Support Vector Machines- SRAM EM/IR analysis- Memory Architecture/IP Development for Machine learning, Deep Learning Applications- Synthesis and Analysis of datapath circuits such as Multipliers, MAC and adders-Pre-silicon debug, circuit design and analysis and functional simulation-Experience with circuit design in advanced technology nodes,such as 14nm, 16nm and 7nm-Paper published in JSSC \"1.4Gsearch/s 2-Mb/mm2 TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%,\" in Journal of Solid-State Circuits, vol. 53, no. 1, pp. 155-163, Jan. 2018-Research interests in energy efficient Hardware architectures/Memory architectures for Deep Neural Networks applications. High Bandwidth Memory architectures for higher throughput and lower power-Machine Learning certification from Stanford university. TECHNICAL SKILLSET:Proficient and hands on experience in the following tools:CAD Tools: Cadence Virtuoso (schematic and layout editor), Simvision, Synopsys Verdi, Cadence Encounter, Cadence Genus, RC compiler, Synopsys DC/Primetime/ICC, Synopsys Star RC.Physical Verification Tools : Synopsys IC Validator and Hercules VUE, MentorGraphics Calibre.Simulators: Cadence Spectre/XPS/APS/UltraSim, Synopsys finesim/HSPICE/hsim. HDL Simulators: Aldec Active-HDL/Riviera-PRO, Xilinx ISE/Vivado, Synopsys VCS, Cadence Verilog-XL,Mentor Graphics Modelsim and Questa.Modelling Tools: MATLAB and Simulink, Synopsys Synphony Model Compiler for FPGA prototyping. Languages: C, C++, Verilog, System Verilog, Java, Python, Perl, Skill, TCL and shell scripting- Familiar with load balancing or job queuing systems for EDA tools, such as LSF.

Experience

1. Sr Silicon Engineer

   Google

   Jun 2022 — Present · Sunnyvale, CA, US

   Silicon Design engineer at google working in the global circuits team in TPU org. Working on SRAMs, SoC Silicon architecture specs and also acting as Lead foundry interface for TPU org.

Education

• Queen's University

  Exchange Scholar, Electrical engineering

  2012 — 2012

• Arizona State University

  Master of Science (MS), Electrical and Electronics Engineering

  2014 — 2016

• Vishwakarma Institute Of Technology

  Bachelor of Technology (BTech), Electrical, Electronics and Communications Engineering

  2010 — 2014

Skills

• Analog
• Scada
• Matlab
• Solar Energy
• Synopsys Tools
• English
• Python
• Wind Turbines
• Functional Verification
• Debugging
• Shell Scripting
• Cadence Encounter
• Power Electronics
• Rtl Design
• Turbines
• C
• Cadence Spectre
• Very-Large-Scale Integration (Vlsi)
• Pcb Design
• Microcontrollers
• Commissioning
• Instrumentation
• Verilog
• Photovoltaics
• Renewable Energy
• Microsoft Excel
• Electronics
• Microsoft Word
• Verification and Validation (V&V)
• Energy
• Microsoft Office
• Vlsi
• Perl Automation
• Cadence Virtuoso
• Electrical Engineering
• Plc
• Cadence
• Energy Management
• Research
• Simulations