Pasupula Supriya
VLSI Engineer at Wipro || Advanced VLSI Design and Verification Trainee Maven Silicon, Bangalore | Seeking for an opportunity in the VLSI Industry | B. Tech(ECE)-2023 Graduate Hyderabad
- Role
- Vlsi Project Engineer at Wipro
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Pasupula Supriya
I am eager to apply my knowledge to real world projects and contribute to cutting edge innovations in VLSI. To gain practical experience and to achieve the goals of the organization.Technical skills HDL : Verilog HVL : System Verilog Verification Methodologies : Constraint Random Coverage Driven Verification Assertion Based Verification –SVA TB Methodology : UVM Protocals : AHP,APBEDA Tool : Modelsim and Mentor Graphics - Questasim Operating System : Linux Core Skills :[RTL Coding using Synthesizable constructs of Verilog | FSM based design Simulation | CMOS Fundamentals Code Coverage | Functional Coverage |Synthesis | Static Timing Analysis | Assertion Based Verification using System Verilog Assertions]Hands on experience : Router 1X3 Design and verification
Experience
Vlsi Project Engineer
Feb 2025 — Present · Bengaluru, IN
Education
Sree Dattaha Group of Institutions
B Tech, ECE
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