Parul Garg
SOC Design Verification Engineer
- Role
- Soc Design Verification Engineer at Intel
- Location
- Patiala, PB, IN
- LinkedIn followers
- 500 followers
Information TechnologyView LinkedIn profile
Experience
Soc Design Verification Engineer
Jul 2024 — Present · Bengaluru, IN
Education
Thapar Institute of Engineering & Technology
Master of Technology - MTech
2022 — 2024
Shiv Nadar University
Bachelor of Technology - BTech
2015 — 2019
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