Parthit Sardhara
RTL Design Engineer at Google
- Role
- Rtl Design Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Parthit Sardhara
8+ years experienced RTL Logic Design Engineer with a demonstrated history of working in the VLSI industry.• Known Protocols : Interconnect, DDR, AMBA AXI4, APB, AXI4 Stream, USB3.x PHY and Link Layer, USB3.1/3.2 Retimer, PIPE 4.3, CSI-2/DSI Video Processing• Skills : RTL Logic design, Micro Architecture, Lint, CDC, Synthesis, Low power design, Debugging, Shell and Perl Scripting• Known Tools : Xcelium, QuestaSim, ActiveHDL, Vivado, Lattice Radiant• Other Interests : Matlab, Physics, Planetary Science, and RF Microwave.
Experience
Rtl Design Engineer
Aug 2024 — Present · Bengaluru, IN
Education
Shree Universal High School
10th
2011 — 2012
Birla Institute of Technology and Science, Pilani
Master of Technology - MTech, Microelectronics
The School of Science - Rajkot
12th
2012 — 2014
Dharmsinh Desai University
Bachelor in Technology, Electrical, Electronics and Communications Engineering
2014 — 2018
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