Partha Sarathi Gujjari

Experience

1. Engineering Manager (Clocking)

   Intel

   Mar 2023 — Present · Hyderabad, IN

Education

• Govt. High School, VNC, Hyderabad

  SSC

  1985 — 1989

• Jawaharlal Nehru Technological University, Hyderabad

  Master of Technology (M.Tech.), VLSI System Design

• Institute of Electronics and Telecommunications Engineering

  BTech, Electronics nd Telecommunications

  2000 — 2005

• QQ Govt. Polytechnic, Hyderabad

  Diploma in Electronics and Communications, ECE

  1994 — 1996

• University of Califonia, SC

  Certification in VLSI Physical Design, VLSI Physical Design

  2007 — 2007

Skills

• Physical Design
• Cadence Virtuoso
• Lvs
• Ic
• Linux
• Rtl Design
• Very-Large-Scale Integration (Vlsi)
• Soc
• Asic
• Scripting
• Timing Closure
• Rc Phy
• Drc
• Timing
• Route
• Systemverilog
• Low-Power Design
• Conformal Lec
• Floorplanning
• Dfm
• Routing
• Clock Tree Synthesis
• Application-Specific Integrated Circuits (Asic)
• Rtl Coding
• Physical Verification
• Design for Manufacturing
• Tcl
• Vlsi
• Cmos
• Ccopt
• Primetime
• Static Timing Analysis
• Semiconductors