Partha Kundu
Chief Architect @Stealth AI Startup
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WORK HISTORY
Chief Architect @Stealth AI Startup
Palo Alto, CA, US
Wafer scale system solution for AI inference workloads using patent pending low power photonics interconnects
EDUCATION
Stony Brook University
MS, Electrical Engineering
Birla Institute of Technology and Science, Pilani
Bachelor of Engineering - BE, Electrical and Electronics Engineering
SKILLS
ABOUT PARTHA KUNDU
Partha Kundu is working on systems and networking problems dealing with scale - currently on system and networking solutions for AI/ML distributed training and inference on Transformer based large language models. Most recently he architected compute and networking solutions for cloud infrastructures for a prominent neo cloud vendor providing secure, virtualized environments for large scale AI/ML training and inference. Priorto that he was responsible for = networking systems for high performance (HPC/Exascale) computing and in the past, on cloud infrastructures and security appliances. Throughout his career Partha has worked on the cutting edge of technology: from the design of the very first superscalar Intel Pentium processor chip to the architecture of the revolutionary Itanium instruction set to the highest performing DEC Alpha microprocessors. As a hands-on technologist he brings experience working with nascent and emerging technologies as well as the ability to develop a view of relevant technology trends and communicate them in the form of a clear, convincing vision and roadmap. He is recognized as one of the earliest contributors to the field of on-chip interconnects, working within the broader community to find a scalable approach to the problem of communication within many core CPUs. Partha Kundu is an engineer and respected thought leader with a strong portfolio of publications, patents, and recognition from leading industry organizations and academia.CAREER HIGHLIGHTS/EXPERTISE • Technology evangelism within company and across industry/academia• Architect of high-performance x86, Itanium, and DEC/Alpha server CPUs• Interconnection network analysis and design (Juniper Clos-based Qfabric)• Ethernet and extensions for the data center (CEE)• Multi-processor cache design (Intel Tukwila)• Network-on-Chip (NoC) expertise• Expert in component-level performance modeling and performance projection (C, C++, SystemC)• Experience with high performance logic design (System Verilog, VCS/ModelSim)• Expertise in power, power management for 65, 32nm CMOS processesSkills & Expertise:Architecture definition, Performance modeling, Cache design, Shared Memory, Interconnection networks, Microprocessors, SoC, Design flow, Low power design, RTL, ASIC, Verilog, micro architecture, Low-power Design, X86, ARM
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