Parth Ramanuj
Memory Layout Design Engineer at Intel Technology
- Role
- Memory Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Memory Design Engineer
Jun 2023 — Present · Bengaluru, IN
Education
Ahmedabad Institute Of Technology
B.E
2011 — 2015
Nirma University, Ahmedabad, Gujarat, India
M.Tech
2017 — 2019
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