Parth Jadvani

About Parth Jadvani

I am a Senior Staff Engineer specializing in Processor-in-Memory (PIM), GPU acceleration, and memory subsystem architecture, with 9+ years of experience delivering high-impact solutions across semiconductor, AI, automotive, and multimedia platforms.My work sits at the intersection of architecture, performance modeling, and hardware–software co-design, where I translate complex system-level ideas into measurable performance, power, and efficiency gains.At Samsung Semiconductor, I lead and contribute to PIM and GPU optimization initiatives, building custom architectural simulators, accelerating LLM and deep learning workloads (cuBLAS, cuDNN, PyTorch), and driving JEDEC-compliant LPDDR5 / DFI memory controller development from specification through validation.Previously, at Qualcomm, AMD, and PathPartner, I delivered camera and vision architecture models, secure media pipelines, and production-grade embedded CV/ML systems on heterogeneous SoCs (ARM, DSP, EVE, GPU).What differentiates me- Architecture-first thinking with hands-on execution- End-to-end ownership: modeling → RTL → firmware → system validation- Deep expertise in performance bottleneck analysis and optimization- Proven ability to work across architecture, RTL, DV, firmware, and product teamsFocus Areas:Processor-in-Memory | GPU & AI Acceleration | Memory Controllers | Embedded Systems | Performance Modeling Bangalore, India | Open to Staff / Principal / Architect-level roles

Experience

1. Senior Staff Engineer

   Samsung Semiconductor

   Aug 2022 — Present · Bengaluru, IN

   Driving Processor-in-Memory (PIM) architecture and system-level optimization for next-generation compute platforms• Designed and extended custom GPGPU-Sim / PIM-Sim models to quantify performance, bandwidth, and data-movement trade-offs• Accelerated LLM and DL workloads by optimizing cuBLAS, cuDNN, and PyTorch execution paths• Contributed to LPDDR5 & DFI memory controller architecture, including specification, RTL development, integration, and validation• Delivered JEDEC-compliant, high-performance memory subsystems through close collaboration with architecture and RTL teams

Education

• CDAC & Gujarat Technological University

  Master of Technology - MTech, VLSI & Embedded System Design

  2014 — 2016

• Gujarat Technological University (GTU)

  Bachelor of Engineering (B.Eng.), Electronics and Communications

  2010 — 2014

Skills

• Embedded C
• Matlab
• Microcontrollers
• Rtos
• Team Management
• C
• C++
• Linux Kernel
• Embedded Linux
• Arduion
• Verilog
• Labview
• Device Drivers
• Arm Cortex-M
• Atmel Avr