Parth Gandhi

About Parth Gandhi

I am self-taught, result oriented and enthusiastic person with a flair for learning things quickly with a goal to ensure that my knowledge is leveraged and utilized in the best possible way to make a contribution to the semiconductor industry.Masters in Electrical and Electronics Engineering with specialization in VLSI/ASIC Design/Verification/ValidationGPA: 3.9 / 4.0Work Done So far:https://github.com/parthrgandhiCOURSE CONTENT HIGHLIGHTS:Logic Design: RTL designing, Static Timing Analysis*, HW description language, functional verification, validation, code coverage, fundamentals of Low Power Design, Digital electronics.Architecture : Cache, Cache Protocols, Virtual Memory, Paging, IA - 32 architecture, Pipeling, Branch prediction, MESI protocol, PCI/PCI express. SKILLS:Programming : Verilog, System Verilog, VHDL, C/C++*, Assembly Language 8085/8051. Scripting : Perl, TCL (Basics)Protocols : PCI, Fundamentals of PCI Express, MESI ProtocolTools : Synopsys Design Tool (Design Compiler), Xilinx ISE, Cadence Virtuoso Design Tools.Hardware : Xilinx Spartan-3E FPGA (XC3S500E).Independent Studies:Data Structure | Algorithms | System VerilogCourse Work: CMOS IC Design | Micro- System Design | Static Timing Analysis | Hierarchical Design Methodologies | Advance Logic DesignContact Details :Email : g••••••••@gmail.com

Experience

1. System Validation Engineer

   Intel

   Nov 2021 — Present · Santa Clara, CA, US

   Worked on DDR5 (RDIMM and MRDIMM) validation across multiple Xeon products, perform experiments to enhance system margins.Collaborated with design, architecture, board, firmware, and manufacturing teams to address issues with memory margins.Led and developed automation and regression workflows for data collection, data analysis, and process correlations to achieve the high throughput of the team.Worked on volume correlation for CPU memory margins across various platforms based on key manufacturing parameters.Identified and filled gaps on CPU process coverage for validation.Worked on providing kill and hold limits to HVM for material based on requirements.Developed POC to improve data-analysis tools and worked with tools engineers for deployment.Documented validation processes, test results, and issue reports, providing detailed feedback for continuous improvement

Education

• Ganpat University

  Bachelor of Technology (B.Tech.), Mechatronics, Robotics, and Automation Engineering

  2007 — 2011

• St. Xavier's High School, Loyola Hall

  Higher Secondary Schooling, Physical Sciences

  2005 — 2007

• California State University-Sacramento

  Master's degree, Electrical and Electronics Engineering

  2015 — 2017

Skills

• Perl
• Virtual Memory
• Dma
• Asic
• Vhdl
• Debugging
• Project Management
• Verilog
• C
• Microsoft Office
• Design
• Manufacturing
• Dsi
• Autocad
• Synopsys Tools
• Matlab
• Cadence Virtuoso
• Usb3.0
• C++
• System Verilog
• Qpi
• Teamwork
• Engineering
• Logic Design
• Pcie
• Cmos