Parth Desai
M.Tech VLSI Design-2022-24 @VIT Chennai
- Role
- Dft Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Parth Desai
I am a passionate and detail-oriented VLSI engineer with a strong academic background in VLSI engineering and looking for full time opportunity in Physical design, Verification,RTL Design. My education includes an M.Tech in VLSI Design from Vellore Institute of Technology. Skilled in Verilog, TCL, Python and tools skills are Cadence Virtuoso, Quartus Prime, Innovus, Genus, and ModelSim, I am eager to apply my theoretical knowledge and practical skills in VLSI design to contribute effectively to cutting-edge projects in the semiconductor industry.
Experience
Dft Engineer
Oct 2024 — Present · Bengaluru, IN
Education
VVP Engineering College - India
Bachelor of Engineering - BE
2018 — 2022
Vellore Institute of Technology (VIT)
Master of Technology - MTech
2022 — 2024
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