Parth Chokhawala

About Parth Chokhawala

Experienced Emulation Engineer with over 11 years of hands-on expertise in pre-silicon verification and system-level emulation. Proven track record in defining and bringing up Hybrid Emulation flows, with deep proficiency in SystemVerilog and industry-leading emulators like Palladium Z1,Z2 & Z3 and ZeBu ZS4 & ZS5 Strong understanding of SoC-level emulation, including bring-up and debug of complex designs across multiple projects. Extensive experience with protocols such as AXI, DDR, PCIe, UCIe, and Ethernet Base-R, and expertise in transactor bring-up at the system level. Skilled in using Verdi, VCS, NCSim, and TRACE32 for effective debug and trace analysis. Led the setup of full-stack Emulation Environments — from build-time flows to runtime infrastructure — across both Palladium and ZeBu platforms. Successfully built and mentored emulation teams from the ground up, enabling scalable and efficient project execution.I am passionate about solving complex verification challenges, optimizing emulation workflows, and enabling faster tape-outs through robust pre-silicon infrastructure.

Experience

1. Asic Engineer Emulation

   Meta

   Feb 2025 — Present · Bengaluru, IN

Education

• Gujarat Technological University (GTU)

  Bachelor of Engineering (B.E.), Electronics & Communicatons

  2014

• Essar International School

  High School

  2008 — 2010

• Delhi Public School

  High School

  2004 — 2008

• Manipal Institute of Technology

  Master of Technology (M.Tech.), Microelectronics

  2016

Skills

• Static Timing Analysis
• Digital Electronics
• Xilinx Ise
• Windows
• Universal Verification Methodology (Uvm)
• C
• Microsoft Office
• Microsoft Word
• Electronics
• Rtl Coding
• Physical Design
• Verilog Hdl
• Verilog
• Rtl Design
• System Verilog
• Microsoft Excel
• Powerpoint
• Microelectronics
• Engineering
• Perl Scripting
• Cadence Virtuoso
• Digital Circuit Design