Parshant Rana

About Parshant Rana

Staff. RTL design Engineer in the ARM CMN (Coherent Mesh Network).• I have worked on Arm CMN S3 (AE) and CMN 700 releases for the CML block features. • Responsible for Microarchitecture and RTL design of Chip-to-Chip blocks, • Working with CHI chip-to-chip, CCIX and CXL protocols.• Responsible for fixing the critical timing paths to reduce the total negative slack of the block.• Write the feature spec for the CMN technical reference manuals (TRM) for different releases.• Debug and fix the RTL bugs that comes in any of the earlier released features.SOC Design Engineer:• Logic design for Intel IP, interact with IP architect and implement new features in RTL.• Responsible for clean RTL delivery to the physical design teams.• Responsible for clean synthesized netlist generation of IPs using Design Compiler.• Verify the RTL against the synthesized netlist using Conformal (LEC).• Verify clock domain crossing (CDC), reset domain crossing (RDC) using Spyglass.• Timing convergence using Design Compiler.• Linting – Cleaning the lint violations from the RTL code using Spyglass Lint (SGLINT).

Experience

1. Staff Design Engineer

   Arm

   Oct 2023 — Present · Austin, TX, US

Education

• YMCAUST

  Bachelor's degree, ECE

  2008 — 2012

• Arizona State University

  Master's degree, Electrical and Electronics Engineering (Analog & Mix Signal IC)

  2016

Skills

• Ic
• Linux
• Very-Large-Scale Integration (Vlsi)
• Unix
• Debugging
• Embedded Systems
• Eda
• Integrated Circuit Design
• Windows
• C
• Shell Scripting
• Physical Design
• Floorplanning
• Cmos
• Integrated Circuits (Ic)
• Cadence Virtuoso
• Hspice
• Innovus Implementation System(Encounter)
• Operating Systems
• Vlsi
• Vhdl
• Virtuoso Skill Language
• Calibre - Drc, Lvs, Pex