Paritosh Narayan Pandey
VLSI Design Enthusiast | ECE Graduate | Advanced VLSI Design & Verification Trainee @ Maven Silicon | Digital Design | RTL Coding | Verilog|SystemVerilog|UVM | Open to VLSI Opportunities
- Role
- Advanced Vlsi Design and Verification Trainee at Maven Silicon
- Location
- Kanpur, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Paritosh Narayan Pandey
Passionate to learn about interesting concepts lying behind the manufacturing of a…
Experience
Advanced Vlsi Design and Verification Trainee
Jun 2024 — Present · Bengaluru, IN
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