Parissa Najdesamii

About Parissa Najdesamii

As part of a company-wide Methodology organization, responsible for enhancing…

Experience

1. Principal Engineer

   高通

   Jan 2012 — Present

   Advanced technology enablement Developed methodology and feature set required to automatically implement complex power grids in multi-voltage domain designs and over several macros and areas with multi-voltage power requirements. Defined methodology for fully automated floor-planning flow based on power intent derived power domains and power mesh requirements. Developed top level and block level floorplan guidelines to seamlessly create abutment SOC designs with power grid, pin and poly alignment to achieve best route-ability and IRDrop. Planned globally distributed power switches for low power/leakage products Worked side by side with standard cell and custom macro designers to ensure power grid plan and library elements are designed for best route-ability, IRDrop and flexibility in Advanced-technology nodes.

Skills

• Asic
• Vlsi
• Cpf/Upf
• Very-Large-Scale Integration (Vlsi)
• Top Level Floorplanning
• Verilog
• Abutment Flow
• Eda
• Timing
• Vhdl
• Functional Verification
• Application-Specific Integrated Circuits (Asic)
• Low Power Systems
• Static Timing Analysis
• Soc
• Lvs
• Csh
• Logic Design
• Systemverilog
• Ic
• Timing Budgeting
• Rtl Design
• Formal Verification
• Floorplan Guidelines
• Power Grid Generation
• Debugging
• Tcl
• Logic Synthesis
• Low-Power Design
• Primetime
• Perl
• Multi-Voltage Domains
• System on a Chip (Soc)
• Dft
• Scripting
• Cadence
• Timing Closure
• Floorplanning
• Physical Design
• Processors