Paridhi Vyas
Senior Silicon Design Engineer AMD
- Role
- Sr Silicon Design Engineer at AMD
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Paridhi Vyas
A VLSI Engineer with hands on experience in Functional Verification at IP and SOC level along with Pre-Silicon Validation on emulation platforms like Zebu and Palladium.
Experience
Sr Silicon Design Engineer
Mar 2022 — Present
Education
VIT University
Master of Technology, VLSI Design
2015 — 2017
Skills
- Public Speaking
- Project Management
- Management
- Lasi
- Microsoft Word
- Cadence Virtuoso
- Microsoft Excel
- Powerpoint
- Cadence Encounter
- Basics of C
- Research
- Verilog
- Cadence Assura
- Basics of Perl
- Modelsim
- Xilinx Ise
- Cadence Rc
- Tanner Eda
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