Paridhee Aggarwal
Specialist in ASIC Verification solutions with a decade of experience in design and building a system environment that contributes to powerful computing infrastructure.
- Role
- Staff Engineer at Arm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Paridhee Aggarwal
About 11+ years of experience in pre-silicon verification of complex IP designs including development, enhancement and maintenance of test bench components.Developed monitors, drivers and response checkers using SystemVerilog to verify designs, also have a hands on UVM methodology.Created test-plans and test-cases with focus on coverage driven methodology.Developed I2C, SPI and APB protocols verification environment using UVM methodology and system verilog.Strong analytical, communication and interpersonal skills with Self Starter Attitude.
Experience
Staff Engineer
Jun 2021 — Present · Bangalore Urban, IN
Education
Punjab Technical University
Engineer's Degree, Electronics and Communications Engineering
2006 — 2010
Skills
- Logic Design
- C/C++
- Integrated Circuit Design
- Vhdl
- I2c
- Fpga
- Asic
- Rtl Coding
- Functional Verification
- Veritas Cluster Server
- Static Timing Analysis
- Digital Electronics
- System Verilog
- Soc
- Physical Design
- Formal Verification
- Ncsim
- Xilinx
- Systemverilog
- Debugging
- Specman
- Uvm
- Logic Synthesis
- Vmm
- Sva
- C++
- Amba Ahb
- Verilog
- C
- Xilinx Ise
- Pcie
- Cadence Virtuoso
- Rtl Design
- Open Verification Methodology
- Perl
- Eda
- Tcl
- Vlsi
- Modelsim
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.