Sushil Pareek
Sr. Manager, Design Verification at Micron Technology
- Role
- Sr Manager at Micron Technology
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Sushil Pareek
Logic Design Engineer. Currently learning device physics, statistics and formal verification.Strong expertise in digital design and verification using System Verilog TestbenchProficient in Perl, SVAGood understanding of UVM Testbench and random stimulus generation, formal verification (jasper cad tools), computer architecture
Experience
Sr Manager
Oct 2025 — Present · San Jose, CA, US
Education
San José State University
Master of Science (M.S.), Electrical Engineering
2012 — 2014
University of Mumbai
Bachelor of Engineering (B.E.), Electronics
2008 — 2012
Skills
- Verilog
- Perl
- Cadence
- Modelsim
- C++
- Jasper
- Java
- Tcl
- Matlab
- Arm
- Formal Verification
- 8051 Assembly
- Cadence Virtuoso
- Unix
- Mac Os
- Vhdl
- Systemverilog
- Synopsys Tools
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.