Madhu Sudan Pareek

About Madhu Sudan Pareek

VLSI professional with experience in high-performance SoC design closure, physical design (RTL to GDSII), timing signoff, and PPA optimization across advanced nodes (3nm–90nm). Skilled in clock tree methodologies, low-power multi-domain design, and automation flows that accelerate turnaround time.I’ve held leadership and technical roles at Rivos, Cadence, Arm, Qualcomm, and Freescale—driving critical tapeouts, developing flows, and mentoring teams. Recognized with multiple customer appreciation awards and industry presentations (CDNLive on Cadence Cerebrus), I thrive at solving complex design challenges and ensuring first-time-right silicon.Passionate about continuous learning, team collaboration, and delivering impact in fast-paced environments.

Experience

1. Silicon Engineer

   Meta

   Dec 2025 — Present · Bengaluru, IN

Education

• Malaviya National Institute of Technology Jaipur

  B. Tech, Electronics & Communication

  2005 — 2009

Skills

• Asic
• Physical Verification
• Design Rule Checking (Drc)
• Low-Power Design
• Soc
• Place & Route
• Power Planning
• Tcl
• Vlsi
• Physical Design
• Eda
• System on a Chip (Soc)
• Floorplanning
• Lvs
• Drc
• First Encounter