Paras Bhanwal

About Paras Bhanwal

Silicon Design & Verification Engineer with specialization in Emulation and FPGA Prototyping.My expertise lies in delivering high-complexity IP and SoC-level emulation builds using ZeBu and Palladium platforms for AMD’s next-generation FPGA products.My responsibility includes -~ RTL to emulation platform development~ Transactor integration and testing~ IP/SoC level testbench development~ Waveform capture and RTL debugs~ Post-silicon bring-up support~ RTL development for RTL feature testing.~ Simulation bring-ups using VCS~ Custom FPGA prototyping setups for IP level designsTechnical Highlights:Emulation/Prototyping: ZeBu, Palladium, and FPGA prototyping builds.Protocols: PCIe, CXS, AXI, and APB.Design & Verification: RTL development, SystemVerilog, transactor integration.Tools & Scripting: VCS, Verdi, Vivado, Python, TCL, and C.

Experience

1. Senior System Design Engineer

   AMD

   Apr 2025 — Present · Hyderabad, IN

   Developed CXL monitor IP for capturing CXL traffic in PL, verified and tested this IP on FPGA at 300Mhz, IP used by multiple validation teams for RTL debugs.– Developed PCIe streaming IP for validating PCIe features, verified and tested this IP at 100MHz.– Used Cline to reduce soft IP development time by 20%.

Education

• Arya College of Engineering and IT

  B.Tech, Electronics and Communications Engineering

  2015 — 2019

• Birla School ,Pilani

  Senior Secondary Education

  2013 — 2015

• Arya College of Engineering & I.T. - India

  Bachelor of Technology, Electrical, Electronics and Communications Engineering

• Dhirubhai Ambani University

  Master of Technology, Electrical, Electronics and Communications Engineering