Parag Goel

About Parag Goel

With almost 16+ years of experience, working as an Emulation Silicon Design Engineer @ AMD.Prior to this worked as a Graphics HW Engineer @ Intel, worked on the functional verification of GPU 3D Graphics pipeline verification in the domain of Shader/Raster IP\'s. Took lead in revamping/scratch building of UVM based verification setup from existing AVM based environment for the aforesaid functional areas.Was working as Senior CAE for almost 7 years @ Synopsys, the worked on various emulation technologies with focus on the emulatable transactor development and deployment. I am involved in setting up of the transaction based flows across various customers involving various TBA techniques like, DPI-based, Native SV and deployment of off the shelf ZeBu transactors. Also work on the advanced methodologies, like VMM and OVM/UVM, and provide relevant solutions to key customers in this space. I have also worked on developing VC VIPs for MIPI based protocols like, MPHY, LLI, Unipro etc. Earlier, I was primarily into ASIC verification using HVLs such as SystemVerilog, and advanced verification methodologies at Transwitch and Applied Micro. I played a key role in the development of verification IP for various standard protocols, especially related to Ethernet switching and AMBA related protocols – AXI/AHB. I also worked on module-level PCI Express verification and PPC side verification in the SoC environment.

Experience

1. Pmts Silicon Design Engineer

   AMD

   Jul 2021 — Present · Bengaluru, IN

Education

• Maharshi Dayanand University

  Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering

  2001 — 2005

• Apeejay School

  12th, Science

  1999 — 2001

Skills

• Asic
• Hardware Architecture
• Open Verification Methodology
• Modelsim
• Pcie
• Ethernet
• Integrated Circuit Design
• Perl
• Systemverilog
• Logic Design
• Verilog
• Functional Verification
• Powerpc
• Coverage Analysis
• Vhdl
• Vcs
• Soc
• Ahb
• Vlsi
• Vmm
• Amba Ahb
• Uvm