Paolo Verrecchia
Design Verification Engineer @Apple
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WORK HISTORY
Design Verification Engineer @Apple
Munich, DE
Work closely with the design and architecture team to develop a comprehensive verification plan. Review specifications, develop attributes, tests and coverage plans, define methodology and test benches. Work with SystemVerilog testbench for block-level and top-level functional verification.
EDUCATION
Sapienza Università di Roma
Electronics
SKILLS
ABOUT PAOLO VERRECCHIA
Specialties: ASIC verification (SystemVerilog, Specman, C, systemC, SVA, PSL, OVM, UVM, eRM), ARM processors. OCP, AMBA (AXI, AHB, APB) protocols.• Languages: SystemVerilog, Specman, VHDL, Verilog, SVA, Perl, TCL, Makefile, C, C++, systemC.• Tools: Questa/Modelsim, Specman, NcSim, Codelink• Versioning: Clearcase, DesignSync, SVN
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